A phase locked loop (PLL) is traditionally used to generate a local oscillator (LO) signal in cellular and non-cellular radio transceivers. One of the key parts of the loop is a voltage controlled oscillator (VCO) generating an output signal which is the LO signal. Current silicon based integrated circuit manufacturing processes enable integrating of all the PLL blocks including the VCO to one chip if the process tolerances are taken into account during a design process. This requires calibrating the tolerances in the production line of the end product or at a suitable time when the device is turned on.
A traditional way to implement a transmitter on a radio application specific integrated circuit (ASIC) is to use a quadrature modulator to produce a radio frequency single sideband signal. A similar radio frequency signal can be also generated by using a so-called direct polar conversion. In these applications, a VCO control voltage is modulated to provide a signal phase modulation. An envelope modulation can be produced, for example, by modulating a power supply of a power amplifier. The polar conversion decreases an area of a transmitter on the ASIC and reduces a power dissipation with a proper design. On the other hand, it sets stringent requirements on individual transmitter block specifications, e.g., a PLL open loop gain variation. A VCO gain is an important parameter describing the open loop gain.
In a receiver, the PLL open loop gain may not be so precisely defined but the VCO just needs to be able to produce the right frequency in a certain tuning voltage range considered safe for the particular design. However, if the settling time of the PLL is needed to be optimized, the VCO gain optimization may be used in the receiver as well.
There are two aspects determining the design problem of integrated VCOs of which the first one is common to all receiver and transmitter architectures utilizing the integrated VCO and the second one is more related to the polar transmitter architecture.
First, the VCO center frequency varies due to the process and temperature variations so much that some coarse tuning of a resonator tank is needed to compensate the variations. The most popular way of doing so is to use a digitally controllable capacitor array in parallel with the resonator coil. Also resonator tuning, in series with the resonator coil or any other control type affecting the VCO center frequency, can be used.
Second, an accurate control of the PLL open loop gain requires controlling several parameters of the loop. One way of implementing the control is to make some measurements using analogue to digital conversions and then calculate calibration coefficients in a digital domain and convert them back to an analog parameter (e.g., a charge pump current) for the open loop gain tuning. The tuning is necessary to meet polar conversion requirements for all possible conditions over the frequency range, e.g., when at least a traditional PLL architecture containing a charge-pump, a passive loop filter and a varactor controlled VCO is utilized. It is well known that when less bits are needed for tuning, it reduces the converter design non-linearity problems arising from a device mismatch. The VCO gain variation range over the frequency band in use will affect requirements set to a DA (digital-to-analog) conversion compensating a VCO gain error effect on the VCO open loop gain.
There are several existing methods for coarse tuning a center frequency of the integrated VCO. However, none of the known prior art methods deal with a VCO gain variation at the same time.